1 Overview of STM32 Basic Knowledge#
1.1 Introduction to STM32#
STM32 is a 32-bit microcontroller developed by STMicroelectronics based on the ARM Cortex-M core.
M stands for Microcontroller.
STM32 is commonly used in embedded fields such as smart vehicles, drones, robots, wireless communication, the Internet of Things, industrial control, and entertainment electronic products.
STM32 is powerful, has excellent performance, rich on-chip resources, and low power consumption, making it a classic embedded microcontroller.
1.2 Introduction to ARM#
ARM refers both to ARM Holdings and ARM processor cores.
ARM Holdings is a leading global semiconductor intellectual property (IP) provider, with over 95% of smartphones and tablets worldwide using ARM architecture.
ARM designs ARM cores, while semiconductor manufacturers enhance the core's peripheral circuits and produce chips.
1.3 Introduction to STM32F103C8T6#
Series: Mainstream series STM32F1
Core: ARM Cortex-M3
Main frequency: 72MHz
RAM: 20K (SRAM)
ROM: 64K (Flash)
Power supply: 2.0~3.6V (Standard 3.3V)
Package: LQFP48
1.4 On-chip Resources/Peripherals#
STM32 can incorporate operating systems such as FreeRTOS, UCOS, etc. If these operating systems are used, SysTick is required to provide timing for task switching.
UART stands for asynchronous serial port, while STM32's USART supports both asynchronous and synchronous serial ports, with asynchronous serial ports being more commonly used.
| Abbreviation | Name | Abbreviation | Name |
|---|---|---|---|
| NVIC | Nested Vector Interrupt Controller | CAN | CAN Communication |
| SysTick | System Tick Timer | USB | USB Communication |
| RCC | Reset and Clock Control | RTC | Real-Time Clock |
| GPIO | General Purpose IO | CRC | CRC Check |
| AFIO | Alternate Function IO | PWR | Power Control |
| EXTI | External Interrupt | BKP | Backup Register |
| TIM | Timer | IWDG | Independent Watchdog |
| ADC | Analog-to-Digital Converter | WWDG | Window Watchdog |
| DMA | Direct Memory Access | DAC | Digital-to-Analog Converter |
| USART | Synchronous/Asynchronous Serial Communication | SDIO | SD Card Interface |
| I2C | I2C Communication | FSMC | Flexible Static Memory Controller |
| SPI | SPI Communication | USB OTG | USB Host Interface |
1.5 Chip Naming Convention#
1.6 System Architecture#
The Cortex-M3 core features three buses: ICode instruction bus, DCode data bus, and System system bus.
The ICode and DCode buses are primarily used to connect to Flash memory.
The Flash stores the programs we write.
The ICode instruction bus is used to load program instructions.
The DCode data bus is used to load data, such as constants and debug data.
The System bus connects to SRAM and FSMC.
SRAM is used to store variable data during program execution.
The AHB system bus is used to mount major peripherals. AHB stands for Advanced High-Performance Bus, typically mounting the most basic or high-performance peripherals, such as reset and clock control circuits, with SDIO also mounted on AHB.
The two peripheral buses APB1 and APB2, where APB stands for Advanced Peripheral Bus, are used to connect general peripherals.
Due to differences in bus protocols, speeds, and data transfer formats between AHB and APB, two bridges are needed for data conversion and buffering. Overall, AHB has higher performance than APB, with APB2 generally having higher performance than APB1. APB2 typically operates at the same frequency as AHB, which is 72MHz, while APB1 usually operates at 36MHz. Therefore, APB2 generally connects to slightly more important peripherals, such as GPIO ports and some key peripherals (USART1, SPI1, TIM1, TIM8, etc.). TIM8, like TIM1, is also a high-end timer, making it an important peripheral. ADC, EXTI, and AFIO are also connected to APB2. Other peripherals like 2, 3, 4, 5, DAC, PWR, and BKP, which are less critical, are allocated to APB1. However, in practice, users generally do not notice performance differences between APB2 and APB1; it is sufficient to know which bus a peripheral is mounted on.
DMA can be thought of as the CPU's little secretary, handling tasks like moving large amounts of data, which would be a waste of time for the CPU. DMA mainly handles these simple and repetitive tasks. DMA connects to the bus matrix via the DMA bus and has the same bus control rights as the CPU to access these peripherals. When data transfer is needed, the peripheral sends a DMA request through the request line, and DMA gains bus control to access and transfer data, all without CPU involvement, saving CPU time for other tasks.
1.7 Pin Definitions#
Red pins are power-related.
Blue pins are related to the minimum system.
Green pins are IO ports and functional pins.
S type represents power.
I type represents input.
O type represents output.
IO type represents input/output.
FT indicates that this pin can tolerate 5V voltage; those without FT can only tolerate 3.3V voltage.
STM32 uses a partitioned power supply method, with multiple power supply pins. When used, VSS is connected to GND, and VDD is connected to 3.3V.
STM32 supports two debugging methods: SWD and JTAG.
SWD requires two lines, SWDIO and SWCLK.
JTAG requires five lines: JTMS, JTCK, JTDI, JTDO, and NJTRST.
STLINK uses the SWD method to download and debug programs, so it only occupies PA13 and PA14 IO ports.
When downloading using SWD, PA15, PB3, and PB4 can be switched to regular IO ports, but this needs to be configured in the program; by default, they will not be used as IO ports.
| Pin Number | Pin Name | Pin Definition | Main Function |
|---|---|---|---|
| 1 | VBAT | Backup battery power pin, this pin can connect to a 3V battery; when the system power is off, the backup battery can power the internal RTC clock and backup register | VBAT |
| 2 | PC13-TAMPER-RTC | I/O port or intrusion detection or RTC; the IO port can output or read high and low levels based on the program; intrusion detection can be used for security functions, RTC can output RTC calibration clock, RTC alarm pulse, or second pulse | PC13 |
| 3,4 | PC14-OSC32_IN/PC15-OSC32_OUT | IO port or connect to a 32.768KHz RTC crystal | PC14/PC15 |
| 5,6 | OSC_IN/OSC_OUT | Connect to the system's main crystal, generally 8MHz; the chip has a phase-locked loop circuit that can multiply this 8MHz frequency to ultimately produce a 72MHz frequency as the system's main clock | OSC_IN/OSC_OUT |
| 7 | NRST | System reset pin, N indicates low-level reset | NRST |
| 8,9 | VSSA/VDDA | Power supply for the internal analog section, such as ADC, RC oscillator, etc.; VSS is negative connected to GND, VDD is positive connected to 3.3V | VSSA/VDDA |
| 10 | PA0-WKUP | IO port with WKUP function, can wake up the STM32 in standby mode | PA0 |
| 11-19 | PA1、PA2、PA3、PA4、PA5、PA6、PA7、PB0、PB1 | IO port | PA1-PB1 |
| 20 | PB2 | IO port or BOOT1 pin; the BOOT pin is used to configure the startup mode | PB2/BOOT1 |
| 21,22 | PB10、PB11 | IO port | PB10，PB11 |
| 23,24 | VSS_1/VDD_1 | Main power supply pin for the system; VSS is negative, VDD is positive | VSS_1/VDD_1 |
| 25-33 | PB12、PB13、PB14、PB15、PA8、PA9、PA10、PA11、PA12 | IO port | PB12、PB13、PB14、PB15、PA8、PA9、PA10、PA11、PA12 |
| 34 | PA13 | IO port or debugging port | JTMS/SWDIO |
| 35,36 | VSS_2/VDD_2 | Main power supply pin for the system; VSS is negative, VDD is positive | VSS_2/VDD_2 |
| 37-40 | PA14/PA15/PB3/PB4 | IO port or debugging port (used for debugging and downloading programs) | JTCK_SWCLK/JTDI/JTDO/NJTRST |
| 41-43 | PB5/PB6/PB7 | IO port | PB5/PB6/PB7 |
| 44 | BOOT0 | Like BOOT1, also used for startup configuration | BOOT0 |
| 45,46 | PB8/PB9 | IO port | PB8/PB9 |
| 47,48 | VSS_3/VDD_3 | Main power supply pin for the system; VSS is negative, VDD is positive | VSS_3/VDD_3 |
1.8 Boot Configuration#
The purpose of boot configuration is to specify where the program starts running. Generally, the program starts executing in the Flash program memory, but in certain cases, we can also let the program start executing from other locations to complete special functions.
BOOT1=0 BOOT0=1 mode is used for serial port downloading; the system memory stores a segment of BootLoader program in STM32. The role of the BootLoader program is to receive data from the serial port and refresh it to the main flash memory, allowing programs to be downloaded via the serial port. Typically, we configure this mode when we need to download programs via the serial port.
BOOT0=0 sets the boot mode to the main flash memory mode, where the main flash memory is selected as the boot area, and the program in the flash memory is executed normally. This mode is the most commonly used mode and is generally the default configuration.
BOOT1=1 BOOT0=1 configures for SRAM boot, mainly used for program debugging and is currently used less frequently.
The value of the BOOT pin is valid at the moment of power-on reset, after which it can be arbitrary.
1.9 Minimum System Circuit#
OSC32 refers to a 32.768KHz crystal oscillator; 32768 is 2 raised to the power of 15, and the internal RTC circuit can generate a 1s time signal through a division of 2 raised to the power of 15.
RTC crystal oscillator is a 32.768KHz crystal.
